Module: Digital & Analogue Electronics II

Module Specifications.

Current Academic Year 2024 - 2025

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Date posted: September 2024

Module Title	Digital & Analogue Electronics II
Module Code	EE201 (ITS) / EEN1016 (Banner)
Faculty	Engineering & Computing	School	Electronic Engineering
Module Co-ordinator	Liam Meany
Module Teachers	-
NFQ level	8	Credit Rating	5
Pre-requisite	Not Available
Co-requisite	Not Available
Compatibles	Not Available
Incompatibles	Not Available

None
Coursework can't be resat in August as it consists of Lab exercises.

Description

To provide the student with a thorough understanding of the principles and practical aspects of modern digital and analogue circuits.

Learning Outcomes

1. Design and construct transistor circuits
2. Analyse and construct combinational and sequential logic circuitry
3. Design and construct basic arithmetic circuitry
4. Describe and explain I/O interfacing in computer systems

*Type*	*Hours*	*Description*
Workload	Full-time hours per semester
Lecture	24	No Description
Tutorial	9	No Description
Laboratory	15	No Description
Independent Study	77	No Description
Total Workload: 125

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

Transistors
BJT basics (NPN, PNP), Biasing, DC & AC analysis, Load-Line, Q-point, Common Emitter configuration v other configurations, Gain, Phase and the use of the transistor as an amplifier.

Combinational Logic
Encoders/Decoders, Multiplexers/Demultiplexers design from gates, Odd & Even Parity and use of Hamming Code for detecting/correcting bit errors.

Binary Arithmetic:
Look-ahead carry adders, Booth's Algorithm Multiplication, Floating point arithmetic & IEEE754 representation, Basic ALU design and construction.

Sequential Logic:
Sequence recogniser design using State Diagram, Next State Table, State Assignment and reduction.

Digital Circuitry:
TTL NAND gate analysis, Logic levels & Noise Immunity, Wired-AND & Tri-State Busing, MOS technologies with reference to speed, power consumption, noise margin, loading and gate construction.

Digital Storage:
Bistable latch, Organisation of memory systems with address decoders, RAM and ROM types.

Programmable Logic Devices:
PLA & PAL logic arrays, use of GAL22v10 device in programmable logic design.

Digital Interfacing:
I2C bus, USB2 communication, SPI, RS232/UART

Assessment Breakdown
Continuous Assessment	25%	Examination Weight	75%

Type	Description	% of total	Assessment Date
Course Work Breakdown
Laboratory Portfolio	5 x 3-hour lab exercises	25%	Every Second Week

Reassessment Requirement Type
Resit arrangements are explained by the following categories: Resit category 1: A resit is available for both* components of the module. Resit category 2: No resit is available for a 100% continuous assessment module. Resit category 3: No resit is available for the continuous assessment component where there is a continuous assessment and examination element.
* ‘Both’ is used in the context of the module having a Continuous Assessment/Examination split; where the module is 100% continuous assessment, there will also be a resit of the assessment
This module is category 3

Indicative Reading List

Tocci, R. J.: 2010, Digital Systems, (11th Edition), Prentice Hall,
Floyd, T. L.: 2013, Digital Fundamentals, Pearson Education,
Katz, R. H.: 2004, Contemporary Logic Design, (2nd Edition), Prentice Hall,
Daniel Page: 2009, A practicel Introduction to Computer Architecture, Springer,
David Harris, Sarah Harris: 2012, Digital Design and Computer Architecture, (2nd Edition), Morgan Kaufmann,
Hambley, Allan: 2011, Electrical Engineering: principles and applications,

Other Resources

23854, DCU Loop, Liam Meany, 2013, Digital and Analogue Electronics II, https://loop.dcu.ie,