Module: Computer Architecture and HDL

Module Specifications..

Current Academic Year 2023 - 2024

Please note that this information is subject to change.

Module Title	Computer Architecture and HDL
Module Code	EE496
School	School of Electronic Engineering
Module Co-ordinator	Semester 1: Xiaojun Wang Semester 2: Xiaojun Wang Autumn: Xiaojun Wang
Module Teachers	Xiaojun Wang Alan Kennedy
NFQ level	8	Credit Rating	5
Pre-requisite	None
Co-requisite	None
Compatibles	None
Incompatibles	None

None
Both CA and Exam are available for reassessment

Description

This module introduces computer architecture through a hardware description language (HDL). The course objectives are: to describe, simulate and synthesis of digital building blocks and an entire processor, such as arithmetic circuits, memories, using VHDL; to introduce the design of processors, covering the central concepts such as the fetch-decode-execute cycle, addressing mode and instruction encoding; Starting from a MIPS instruction set architecture, gradually expanding on the details, issues and techniques in modern, high-performance processor designs. Processor performance analysis.

Learning Outcomes

1. Describe computer architecture concepts and building blocks
2. Solve new computer architecture design problems within design constraints
3. Assess various design alternatives with quantitative and/or qualitative performance analysis
4. Develop synthesizable register transfer level VHDL models for designs of varying complexity

*Type*	*Hours*	*Description*
Workload	Full-time hours per semester
Lecture	24	Digital design in VHDL, Computer Architecture
Assignment Completion	24	Assignment 1: VHDL modelling, simulation and synthesis
Assignment Completion	48	Assignment 2: VHDL design of a RISC processor
Independent Study	29	preview and review of course content
Total Workload: 125

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

Hardware Description Language
Introduction to VHDL, VHDL for combinational logic design, sequential logic design and Finite State Machines (FSM)

Digital Building Blocks
Adder/subtractor, comparators, ALU, shifter and rotators, multiplication, division, counters, shift registers, memory arrays

Computer Architecture
Instruction set architecture, MIPS microarchitecture, single-cycle processors, multicycle processor, pipelined processors, resolving hazards, performance analysis

Memory systems
caches, virtual memory, memory-mapped I/O, memory system performance analysis

Assessment Breakdown
Continuous Assessment	50%	Examination Weight	50%

Type	Description	% of total	Assessment Date
Course Work Breakdown
Assignment	Assignment 1: Register transfer lever VHDL modelling of combinational and sequential digital building blocks	20%	Week 5
Assignment	Assignment 2: VHDL modelling, simulation and synthesis of a RISC processor.	30%	Week 10

Reassessment Requirement Type
Resit arrangements are explained by the following categories; 1 = A resit is available for all components of the module 2 = No resit is available for 100% continuous assessment module 3 = No resit is available for the continuous assessment component
This module is category 1

Indicative Reading List

David Harris, Sarah Harris,: 2013, Digital Design and Computer Architecture, Second Edition, 2nd, Elsevier, 978-0-12-394424-5
Volnei A. Pedroni: 2010, Circuit Design and Simulation with VHDL, 2nd, MIT Press, 10: 0262014335

Other Resources

43189, Website, NANDLAND, 0, VHDL tutorials, https://www.nandland.com/vhdl/tutorials/index.html, 43190, Website, Weijun Zhang, 2001, VHDL tutorial: learn by example, http://esd.cs.ucr.edu/labs/tutorial/,

Programme or List of Programmes

ECE	BEng Electronic & Computer Engineering
ECEI	BEng Electronic & Computer Engineering
ECSAO	Study Abroad (Engineering & Computing)
ECT	BSc in Electronic & Comp.Technology

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