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Module Specifications.

Current Academic Year 2024 - 2025

All Module information is indicative, and this portal is an interim interface pending the full upgrade of Coursebuilder and subsequent integration to the new DCU Student Information System (DCU Key).

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Date posted: September 2024

Module Title Computer Architecture & HDL
Module Code EE496 (ITS) / EEN1056 (Banner)
Faculty Engineering & Computing School Electronic Engineering
Module Co-ordinatorXiaojun Wang
Module Teachers-
NFQ level 8 Credit Rating 5
Pre-requisite Not Available
Co-requisite Not Available
Compatibles Not Available
Incompatibles Not Available
None
Both CA and Exam are available for reassessment
Description

This module introduces computer architecture through a hardware description language (HDL). The course objectives are: to describe, simulate and synthesis of digital building blocks and an entire processor, such as arithmetic circuits, memories, using VHDL; to introduce the design of processors, covering the central concepts such as the fetch-decode-execute cycle, addressing mode and instruction encoding; Starting from a MIPS instruction set architecture, gradually expanding on the details, issues and techniques in modern, high-performance processor designs. Processor performance analysis.

Learning Outcomes

1. Describe computer architecture concepts and building blocks
2. Solve new computer architecture design problems within design constraints
3. Assess various design alternatives with quantitative and/or qualitative performance analysis
4. Develop synthesisable register transfer level SystemVerilog models for digital designs of varying complexity



Workload Full-time hours per semester
Type Hours Description
Lecture24Digital design in SystemVerilog, Computer Architecture
Independent Study50Preview and review of course content
Directed learning12Installation and get familiar with the Vivado design tool
Assignment Completion39SystemVerilog design of a RISC processor
Total Workload: 125

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

Hardware Description Language
Introduction to SystemVerilog, SystemVerilog for combinational logic design, sequential logic design and Finite State Machines (FSM)

Digital Building Blocks
Adder/subtractor, comparators, ALU, shifter and rotators, multiplication, division, counters, shift registers, memory arrays

Computer Architecture
Instruction set architecture, RISC microarchitecture, single-cycle processors, multicycle processor, pipelined processors, resolving hazards, performance analysis

Memory systems
Caches, virtual memory, memory-mapped I/O, memory system performance analysis

Assessment Breakdown
Continuous Assessment25% Examination Weight75%
Course Work Breakdown
TypeDescription% of totalAssessment Date
AssignmentSystemVerilog modelling, simulation and synthesis of a RISC processor.25%Week 10
Indicative Reading List

  • David Harris, Sarah Harris,: 2013, Digital Design and Computer Architecture, Second Edition, 2nd, Elsevier, 978-0-12-394424-5
  • Volnei A. Pedroni: 2010, Circuit Design and Simulation with VHDL, 2nd, MIT Press, 10: 0262014335
Other Resources

65271, Website, NANDLAND, 0, VHDL tutorials, https://www.nandland.com/vhdl/tutorials/index.html, 65272, Website, Weijun Zhang, 2001, VHDL tutorial: learn by example, http://esd.cs.ucr.edu/labs/tutorial/,

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