Module: Real-Time Digital Signal Processing (DSP)

Module Specifications.

Current Academic Year 2024 - 2025

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Date posted: September 2024

Module Title	Real-Time Digital Signal Processing (DSP)
Module Code	EE515 (ITS) / EEN1073 (Banner)
Faculty	Engineering & Computing	School	Electronic Engineering
Module Co-ordinator	Prince Anandarajah
Module Teachers	-
NFQ level	9	Credit Rating	7.5
Pre-requisite	Not Available
Co-requisite	Not Available
Compatibles	Not Available
Incompatibles	Not Available

None

Description

This module will provide students with the knowledge, skills and competencies in the area of high-speed DSP. It is focused on providing students with not only a strong theoretical foundation, but also the ability to make practical use of modern DSP approaches.

Learning Outcomes

1. Demonstrate a mastery and detailed appreciation of the theoretical founding principles, central algorithms and current implementation-focussed technology of DSP.
2. Categorize the different classes of problems in DSP, and to decide upon appropriate methodologies and technologies for their solution.
3. Design and implement algorithmic solutions for solving advanced DSP problems.
4. Design and implement DSP algorithms for real-time applications.
5. Establish and categorize hardware/software boundaries in DSP
6. Define embedded systems with consideration to cost, power, accuracy and other constraints.
7. Conduct literature searches, abstract and summarize relevant ideas and techniques in DSP- related areas, and demonstrate scientific report writing to as Masters level.
8. Demonstrate the use of analysis and presentation packages relevant to DSP.

*Type*	*Hours*	*Description*
Workload	Full-time hours per semester
Lecture	36	Lectures
Assignment Completion	30	Assignment 1
Assignment Completion	30	Assignment 2
Independent Study	92	Study of module materials and assessment preparation
Total Workload: 188

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

A review of DSP fundamentals
ADC, DACs, Nyquist criteria, Aliasing; Fixed point and floating point number representations; Time-domain and Frequency-domain representation of discrete-time signals, Linear time-invariant systems in the transform domain, Transfer functions; Convolution, Correlation, Windowing operations; Applications of DSP, Low cost DSP, Power efficient DSP, High performance DSP.

Quadrature and multi-rate signal processing
The Hilbert transform; waveform modulation; waveform detection/demodulation; envelope detection and rectification; quadrature frequency translation; decimation; interpolation; base-band sampling; IF and under sampling, frequency shift and recovery.

Real-time Systems:
Real-time systems (soft and hard real time systems, differences between real time and time shared systems, real time event characteristics) Efficient execution (resource management), Challenges in real time systems, Distributed and multiprocessor architectures, Embedded systems.

Embedded Systems and DSP:
Introduction to embedded systems, hardware gates, software programmable, general purpose processors, microcontrollers, FPGA enabled solutions

Hardware for DSP
FPGA in embedded design, ASICs vs FPGAs, Software programmable DSP, General purpose embedded cores; Accuracy vs complexity

DSP Programmable Architectures (DSPPA):
Common features of DSPPA (DSP core and Instruction Set Architecture features, Memory architecture (access sizes and alignment issues), data operations.

Case Studies
Examples include: DSP for IoT, DSP for SDR, LTE baseband software design, MIMO systems, Beamforming for WIMAX

Assessment Breakdown
Continuous Assessment	30%	Examination Weight	70%

Type	Description	% of total	Assessment Date
Course Work Breakdown
Assignment	Design of a DSP chain based on featured content and/or case studies.	15%	Once per semester
Report(s)	Detailed report writing on the applications of DSP processes in selected industry fields.	15%	Once per semester

Reassessment Requirement Type
Resit arrangements are explained by the following categories: Resit category 1: A resit is available for both* components of the module. Resit category 2: No resit is available for a 100% continuous assessment module. Resit category 3: No resit is available for the continuous assessment component where there is a continuous assessment and examination element.
* ‘Both’ is used in the context of the module having a Continuous Assessment/Examination split; where the module is 100% continuous assessment, there will also be a resit of the assessment
This module is category 1

Indicative Reading List

Robert Oshana: 2012, DSP for Embedded and Real-Time Systems, 1st, Newnes, 978-012386535

Other Resources

23066, Website, 0, Module Loop Website, loop.dcu.ie,