Module: HDL & High-Level Logic Synthesis

Module Specifications.

Current Academic Year 2024 - 2025

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Date posted: September 2024

Module Title	HDL & High-Level Logic Synthesis
Module Code	EE540 (ITS) / EEN1000 (Banner)
Faculty	Engineering & Computing	School	Electronic Engineering
Module Co-ordinator	-
Module Teachers	-
NFQ level	9	Credit Rating	7.5
Pre-requisite	Not Available
Co-requisite	Not Available
Compatibles	Not Available
Incompatibles	Not Available

Repeat examination
Array

Description

As system complexity increases, a high-level, top-down design approach becomes essential. The understanding of the top-down design process, and the effective use of standard hardware description languages such as VHDL is therefore important for digital designers. This module introduces the students to the area of high-level logic synthesis from Hardware Description Languages (HDL). It covers HDL modelling for simulation and synthesis, the top-down design process, and the high-level synthesis algorithms that transform an HDL description to its corresponding logic circuits.

Learning Outcomes

1. Write behaviour VHDL models for simulation
2. Write RTL VHDL models for synthesis
3. Use the high-level synthesis techniques
4. Use HDL simulation and synthesis tools
5. Design Digital circuits for implementation with FPGA or ASIC

*Type*	*Hours*	*Description*
Workload	Full-time hours per semester
Lecture	36	3 hours a week
Laboratory	12	Six 2-hour lab session
Assignment Completion	36	An assignment to write a VHDL model according to a design specification, simulate and synthesis the VHDL model
Independent Study	100	Self study on the subject
Directed learning	3	End of Module Formal Examination
Total Workload: 187

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

The evolution of VHDL as an industry standard

VHDL descriptive capabilities

basic VHDL model structure

VHDL modelling styles

modelling of combinational logic

modelling of synchronous sequential logic

simulation cycles

modelling of signal delays

modelling of finite state machines

high-level synthesis from HDL

Design abstraction levels and representation domains

top-down design process

high-level synthesis techniques

control flow graph

data flow graph

high level transformations

scheduling and allocation algorithms

Assessment Breakdown
Continuous Assessment	0%	Examination Weight	0%

Type	Description	% of total	Assessment Date
Course Work Breakdown
Project	An assignment to write a VHDL model according to a design specification, simulate and synthesis the VHDL model	25%	Week 12

Reassessment Requirement Type
Resit arrangements are explained by the following categories: Resit category 1: A resit is available for both* components of the module. Resit category 2: No resit is available for a 100% continuous assessment module. Resit category 3: No resit is available for the continuous assessment component where there is a continuous assessment and examination element.
* ‘Both’ is used in the context of the module having a Continuous Assessment/Examination split; where the module is 100% continuous assessment, there will also be a resit of the assessment
This module is category -

Indicative Reading List

Course notes: 0, available online,
Bhasker, J.: 1996, A VHDL Synthesis Primer, Star Galaxy Publishing, 0965039102
Bhasker, J.: 1994, A VHDL Primer, Prentice Hall, 0131814478
Gajski, D., N. Dutt, A. wu, S. Lin: 1992, High-level synthesis : introduction to chip and system design, Kluwer Academic, 0792391942

Other Resources

None