Latest Module Specifications
Current Academic Year 2025 - 2026
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Description To provide students with advanced knowledge of semiconductor device manufacturing as it relates to CMOS integrated circuits and advanced packaging techniques; including process flows, integration considerations, design aspects and statistical methods. Technology CAD (TCAD) will form an integral component of the module. Students will be able to apply knowledge to device fabrication as it relates to other technologies such as photonic integrated circuits (PICs), micro-electromechanical systems (MEMS) and microfluidic applications. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Learning Outcomes | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml |
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Indicative Content and Learning Activities
Semiconductor industry Technology trends, market dynamics and process overview. Crystal growth Czochralski and Float Zone methods; impurity segregation; crystal defects. Impurity control Factory configuration; wafer cleaning, FEOL/RCA clean, BEOL clean; Gettering Lithography Contact, proximity and projection systems; diffraction regimes (Fresnel and Fraunhofer); aerial image and optical system characterisation; photoresists, DNQ/CAR, latent image; resolution enhancement techniques Oxidation Deal-Grove model, limits and kinetic dependencies; interface and electrical defects; CV measurements; high-k dielectrics. Diffusion Fick’s Laws, analytical approximations, modifications for electric field effects and concentration dependent diffusion; segregation and pile-up; atomic scale mechanisms. Ion implantation Implant profiles; nuclear and electronic stopping; Monte Carlo simulations; annealing, rapid thermal anneal (RTA); transient enhanced diffusion (TED). Etching Wet etching; plasma sheath and chemistry; plasma etching, isotropic, ion milling, ion-enhanced chemical and ion-enhanced inhibitor etching; plasma etching issues; atomic layer etching; chemical mechanical planarisation (CMP). Deposition Chemical vapour deposition (CVD, LPCVD, MOCVD, PECVD); atomic layer deposition (ALD); sputtering; evaporation; epitaxial techniques (ELO and MBE). Interconnect and packaging Signal (SI) and power (PI) integrity; material and process techniques for Al, Cu and low-k dielectrics; system in package (SiP) vs system on chip (SoC), multi-chip modules, chiplets, interposers, 2.5D/3D integrated circuits. Yield Engineering Fundamentals of statistics; distributions (discrete, Normal, Exponential, Chi-squared, t, F); analysis of variance (ANOVA) and hypothesis testing; functional and parametric yield modelling; design centering. Metrology and control Process metrology for wafer and equipment state; statistical process control (SPC), control charts and multivariate control; advanced process control (APC), run-by-run, multivariate and supervisory control | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Indicative Reading List Books:
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Other Resources None | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||