| Module Title |
CMOS Analog Integrated Circuit Design |
| Module Code |
EEN1104 |
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Faculty |
Engineering & Computing |
School |
Electronic Engineering |
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NFQ level |
9 |
Credit Rating |
7.5 |
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Description
The module equips the student with the theoretical knowledge and practical skills to specify, design, simulate, layout and verify CMOS analog integrated circuits. Industry electronic design automation (EDA) tools and standard process design kits (PDKs) are used.
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Learning Outcomes
1. Critically analyse and model CMOS circuits using long- and short-channel analytical approaches, evaluating the validity and limitations of these models in the context of contemporary design practice.
2. Apply and interpret the gm/Id design methodology to realise circuits in advanced CMOS technology nodes, justifying design decisions with quantitative reasoning.
3. Design and implement analogue integrated circuit layouts that mitigate state-of-the-art process limitations, and perform post-layout verification to evaluate performance against design targets.
4. Evaluate and optimise circuit topologies with respect to noise, power, bandwidth and linearity constraints, demonstrating how design trade-offs affect overall system performance.
5. Formulate a specification for a constituent analog block of a complex mixed signal system. Synthesise the circuit and undertake a peer review to critique the design implementation with respect to the target specification.
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| Workload | Full time hours per semester | | Type | Hours | Description |
|---|
| Lecture | 24 | Class based instruction on analysis and design of circuits in a contemporary CMOS process. | | Tutorial | 12 | Problem-based learning relating to analysis and design of circuits. | | Laboratory | 24 | Modelling of gm/Id approach and CAD exercises demonstrating the EDA tools. | | Assignment Completion | 48 | Challenge based learning (CBL) assignment to design a medium complexity circuit. Students will be given an application context within which they will have to formulate a specification, research potential circuit topologies, implement, verify and participate in a peer review critique of their design. | | Independent Study | 79.5 | Self-directed study of lecture materials, literature and homework exercises. |
| Total Workload: 187.5 |
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| Section Breakdown | | CRN | 12181 | Part of Term | Semester 1 | | Coursework | 25% | Examination Weight | 75% | | Grade Scale | 40PASS | Pass Both Elements | N | | Resit Category | RC1 | Best Mark | N | | Module Co-ordinator | Donnacha Lowney | Module Teacher | |
| | Section Breakdown | | CRN | 12203 | Part of Term | Semester 1 | | Coursework | 25% | Examination Weight | 75% | | Grade Scale | 40PASS | Pass Both Elements | N | | Resit Category | RC1 | Best Mark | N | | Module Co-ordinator | Donnacha Lowney | Module Teacher | |
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| Assessment Breakdown |
| Type | Description | % of total | Assessment Date |
|---|
| Assignment | Design project. Students will review the literature pertaining to an assigned circuit e.g. comparator/OTA, formulate a specification, design, implement and characterise their IP block. | 25% | Sem 1 End | | Formal Examination | End of semester examination. | 75% | End-of-Semester |
| Reassessment Requirement Type |
Resit arrangements are explained by the following categories;
RC1: A resit is available for both* components of the module.
RC2: No resit is available for a 100% coursework module.
RC3: No resit is available for the coursework component where there is a coursework and summative examination element.
* ‘Both’ is used in the context of the module having a coursework/summative examination split; where the module is 100% coursework, there will also be a resit of the assessment
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Pre-requisite |
None
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Co-requisite |
None |
| Compatibles |
None |
| Incompatibles |
None |
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All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml
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Indicative Content and Learning Activities
Review of CMOS Technology
P-N junctions.
MOS transistors.
Passive components.
Device modelling
Operating point.
Small-signal models.
Limitations.
gm/Id methodology.
Single stage amplifiers
Common-source.
Source-follower.
Common-gate.
Cascodes and gain boosting.
Output stages.
Differential amplifiers
DC/AC analysis.
Passive and active loads.
Telescopic diff-amp.
Folded cascode diff-amp.
Mismatch and offset effects.
References
Basic current mirror.
Cascoded current mirror.
PTAT and CTAT current sources.
Voltage reference.
Matching.
Feedback
Topologies: shunt-shunt, series-series, series-shunt, shunt-series.
Loading effects.
Return ratio.
Operational amplifiers
Two-stage op amp DC/AC analysis.
Gain boosting.
Compensation and stability.
Slew rate.
Noise.
Common mode feedback.
Power supply rejection.
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Indicative Reading List
Books:
- R. Jacob Baker: 2019, CMOS, John Wiley & Sons, 1284, 978-1-1194-8151-5
- Paul G. A. Jespers,Boris Murmann: 2017, Systematic Design of Analog CMOS Circuits Using Pre-Computed Lookup Tables, Cambridge University Press, 339, 978-1-107-19225-6
- Phillip E. Allen,Douglas R. Holberg: 2012, CMOS Analog Circuit Design, 3rd, Oxford University Press, 608, 978-0199937424
- Paul R. Gray,Paul J. Hurst,Stephen H. Lewis,Robert G. Meyer: 2024, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, 981, 978-1-3942-2006-9
- Behzad Razavi: 2004, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill Education, 9780070529038
- Willy M. C. Sansen: 2006, Analog Design Essentials, Springer Science & Business Media, 796, 978-0-3872-5746-4
- Paul Jespers: 2009, The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits, Springer, 171, 978-0-387-47100-6
Articles:
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Other Resources
- 1: Journal, IEEE, Journal of Solid-State Circuits,
- 419702: 1, Journal, IEEE, Transactions on Circuits and Systems I: Regular Papers,
- https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919: 419703, 1, Journal, IEEE, Transactions on Circuits and Systems II: Express Briefs
- https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8920:
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