| Module Title |
HDL & High-Level Logic Synthesis |
| Module Code |
EEN1000 (ITS: EE540) |
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Faculty |
Electronic Engineering |
School |
Engineering & Computing |
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NFQ level |
9 |
Credit Rating |
7.5 |
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Description
As system complexity increases, a high-level, top-down design approach becomes essential. The understanding of the top-down design process, and the effective use of standard hardware description languages such as VHDL is therefore important for digital designers. This module introduces the students to the area of high-level logic synthesis from Hardware Description Languages (HDL). It covers HDL modelling for simulation and synthesis, the top-down design process, and the high-level synthesis algorithms that transform an HDL description to its corresponding logic circuits.
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Learning Outcomes
1. Write behaviour VHDL models for simulation
2. 1D646EB8-BB1B-0001-2E19-1E6050D96800
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| Workload | Full time hours per semester | | Type | Hours | Description |
|---|
| Lecture | 36 | 3 hours a week | | Laboratory | 12 | Six 2-hour lab session | | Assignment Completion | 36 | An assignment to write a VHDL model according to a design specification, simulate and synthesis the VHDL model | | Independent Study | 100 | Self study on the subject | | Directed learning | 3 | End of Module Formal Examination |
| Total Workload: 187 |
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| Section Breakdown | | CRN | 11338 | Part of Term | Semester 1 | | Coursework | 0% | Examination Weight | 0% | | Grade Scale | | Pass Both Elements | Y | | Resit Category | | Best Mark | N | | Module Co-ordinator | | Module Teacher | |
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| Assessment Breakdown |
| Type | Description | % of total | Assessment Date |
|---|
| Project | An assignment to write a VHDL model according to a design specification, simulate and synthesis the VHDL model | 25% | Week 12 | | Formal Examination | End-of-Semester Final Examination | 75% | End-of-Semester |
| Reassessment Requirement Type |
Resit arrangements are explained by the following categories;
RC1: A resit is available for both* components of the module.
RC2: No resit is available for a 100% coursework module.
RC3: No resit is available for the coursework component where there is a coursework and summative examination element.
* ‘Both’ is used in the context of the module having a coursework/summative examination split; where the module is 100% coursework, there will also be a resit of the assessment
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Pre-requisite |
None
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Co-requisite |
None |
| Compatibles |
None |
| Incompatibles |
None |
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All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml
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Indicative Content and Learning Activities
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Indicative Reading List
Books:
- Course notes: 0, available online,
- Bhasker, J.: 1996, A VHDL Synthesis Primer, Star Galaxy Publishing, 0965039102
- Bhasker, J.: 1994, A VHDL Primer, Prentice Hall, 0131814478
- Gajski, D., N. Dutt, A. wu, S. Lin: 1992, High-level synthesis : introduction to chip and system design, Kluwer Academic, 0792391942
Articles:
None |
Other Resources
None |
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